 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| EM78P153E OTP ROM 1. GENERAL DESCRIPTION EM78P153E is an 8-bit microprocessor with low-power and high-speed CMOS technology. It is equipped with a 512*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a PROTECTION bit to prevent intrusion of user's code in the OTP memory as well as 15 OPTION bits to match user's requirements. With its OTP-ROM feature, the EM78P153E offers users a convenient way of developing and verifying their programs. Moreover, user developed code can be easily programmed with the EMC writer. This specification is subject to change without prior notice. 1 2002/03/01 EM78P153E OTP ROM 2. FEATURES * 14-lead packages : EM78P153E * Operating voltage range : 2.3V~5.5V * Available in temperature range: 0C~70C * Operating frequency rang (base on 2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V. * Low power consumption: * less then 1.5mA at 5V/4MHz * typical of 15 A, at 3V/32KHz * typical of 1 A, during the sleep mode * 512 x 13 bits on chip ROM * Three built-in calibrated IRC oscillators * Programmable prescaler of oscillator set-up time * On-board bit by bit programming * One security register to prevent the code in the OTP memory from intruding * One configuration register to match the user's requirements * 32x 8 bits on chip registers (SRAM, general purpose register) * 2 bi-directional I/O ports * 5 level stacks for subroutine nesting * 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt * Power down mode (SLEEP mode) * Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt * Programmable free running watchdog timer * 7 programmable pull-high I/O pins * 7 programmable open-drain I/O pins * 6 programmable pull-down I/O pins * Two clocks per instruction cycle * 99.9% single instruction cycle commands This specification is subject to change without prior notice. 2 2002/03/01 EM78P153E OTP ROM * Package types: * 14 pin DIP 300mil: EM78P153EP * 14 pin SOP 150mil: EM78P153EN * The transient point of system frequency between HXT and LXT is around 400KHz. This specification is subject to change without prior notice. 3 2002/03/01 EM78P153E OTP ROM 3. PIN ASSIGNMENTS P50 P67 P66 Vdd P65/OSCI P64/OSCO P63//RST 1 2 EM78P153E 14 13 12 11 P51 P52 P53 Vss P60//INT P61 P62/TCC 3 4 5 6 7 10 9 8 Fig. 1 Pin Assignment Table 1 Pin Description Symbol Vdd P65/OSCI Pin No. 4 5 Type I/O Function Power supply. * General purpose I/O pin. * External clock signal input. * Input pin of XT oscillator. * Pull_high/open-drain * Wake up from sleep mode when the status of the pin changes. * General purpose I/O pin. * External clock signal input. * Input pin of XT oscillator. * Pull_high/open-drain * Wake up from sleep mode when the status of the pin changes. * If set as /RESET and remain at logic low, the device will be under reset. * If P63 is set and kept at logic "high," the oscillator will oscillate. * If kept at logic low, it cannot oscillate. * Wake up from sleep mode when the status of the pin changes. * Voltage on /RESET must not exceed Vdd during the normal mode. * Pull_high is on if defined as /RESET. * P63 is input pin only * General purpose I/O pin. * Pull_high/open_drain/pull_down. * Wake up from sleep mode when the status of the pin changes. * External Timer/Counter input. * General purpose I/O pin. * Pull_high/open_drain/pull_down. * Wake up from sleep mode when the status of the pin changes. * Schmitt Trigger input during programming mode * General purpose I/O pin. * Pull_high/open_drain/pull_down. 4 2002/03/01 P64/OSCO 6 I/O P63/RESET 7 I P62/TCC 8 I/O P61 P60//INT 9 10 I/O I/O This specification is subject to change without prior notice. EM78P153E OTP ROM P66, P67 P50~P52 P53 VSS 2, 3 1,14,13 12 11 I/O I/O I/O - * Wake up from sleep mode when the status of the pin changes. * Schmitt Trigger input during the programming mode. * External interrupt pin triggered by falling edge. * General purpose I/O pin. * Pull-high/open-drain. * Wake up from sleep mode when the status of the pin changes. * General purpose I/O pin. * Pull-down * General purpose I/O pin. * Ground. This specification is subject to change without prior notice. 5 2002/03/01 EM78P153E OTP ROM 4. FUNCTION DESCRIPTION OSCO OSCI Oscillator/Timing Control /RESET WDT timer Prescaler TCC /INT ROM R2 Stack Built-in OSC RAM Interrupt Controller R1(TCC) Instruction Register R3 ALU R3 Instruction Decoder ACC DATA & CONTROL BUS P60 P61 P62/TCC P63/REST P64/OSCO P65/OSCI P66 P67 IOC6 R6 I/O PORT 6 Fig. 2 Function Block Diagram 4.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register (R4). 2. R1 (Time Clock /Counter) * Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. * Writable and readable as any other registers. * Defined by resetting PAB(CONT-3). * The prescaler is assigned to TCC if the PAB bit (CONT-3) is reset. * The contents of the prescaler counter is cleared only when a value is written to TCC register. This specification is subject to change without prior notice. 6 2002/03/01 EM78P153E OTP ROM 3. R2 (Program Counter) & Stack * Depending on the device type, R2 and hardware stack are 9-bit wide. The structure is depicted in Fig.3. * 512x13 bits on-chip OTP ROM addresses to the relative p rogramming instruction codes. One program page is 512 words long. * R2 is set as all "0"s when under RESET condition. * "JMP" instruction allows direct loading of the lower 9 program counter bits. Thus, "JMP" allows PC to go to any location within a page. * "CALL" instruction loads the lower 9 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. * "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. * "ADD R2,A" allows the contents of `A' to be added to the current PC, and the ninth of the PC are cleared. * "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth bits of the PC are cleared. * Any instruction that is written to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",) will cause the ninth bits (A8) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. * All instructions are single instruction cycle (fclk/2 or fclk/4), except for the instruction that would change the contents of R2. This instruction will need one more instruction cycle. CALL PC 00 A8 A7 ~ A0 RET RETL RETL K 00 000 1FF Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Page 0 Fig. 3 Program Counter Organization This specification is subject to change without prior notice. 7 2002/03/01 EM78P153E OTP ROM 00 01 02 03 04 05 06 R0 R1(TCC) R2(PC) R3(Status) R4(RSR) R5(Port5) R6(Port6) Stack (5 levels) IOC5 IOC6 CONT 0B 0C 0D 0E 0F RF IOCB IOCC IOCD IOCE IOCF R10 . . . . General Registers R2F Fig. 4 Data Memory Configuration This specification is subject to change without prior notice. 8 2002/03/01 EM78P153E OTP ROM 4. R3 (Status Register) 7 RST 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C * Bit 0 (C) Carry flag * Bit 1 (DC) Auxiliary carry flag * Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. * Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. * Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT time-out. * Bit5 ~ 6 (GP0 ~ 1) General-purpose read/write bits. * Bit 7 (RST) Bit for reset type. Set to 1 if wake-up from sleep mode on pin change. Set to 0 if wake-up from other reset types 5. R4 (RAM Select Register) * Bits 0~5 are used to select registers (address: 00~06, 0F~2F) in the indirect addressing mode. * Bits 6~7 are general-purpose read/write bits. * See the configuration of the data memory in Fig. 4. 6. R5 ~ R6 (Port 5 ~ Port 6) * R5 and R6 are I/O registers. * Only the lower 4 bits of R5 are available. * The upper 4 bits of R5 are fixed to 0. * P63 is input only. 7. RF (Interrupt Status Register) 7 6 5 4 3 2 EXIF 1 ICIF 0 TCIF "1" means interrupt request, and "0" means no interrupt occurs. * Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC overflows, reset by software. * Bit 1 (ICIF) Port 6 input status changed interrupt flag. Set when Port 6 input changes, reset by software. * Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. This specification is subject to change without prior notice. 9 2002/03/01 EM78P153E OTP ROM * Bits 3 ~ 7 Not used. * RF can be cleared by instruction but cannot be set. * IOCF is the interrupt mask register. * Note that the result of reading RF is the "logic AND" of RF and IOCF. 8. R10 ~ R2F * All of these are the 8-bit general-purpose registers. 4.2 Special Purpose Registers 1. A (Accumulator) * Internal data transfer, or instruction operand holding * It can not be addressed. 2. CONT (Control Register) 7 PSR2 0 0 0 0 1 1 1 1 6 /INT PSR1 0 0 1 1 0 0 1 1 5 TS 4 TE PSR0 0 1 0 1 0 1 0 1 3 PAB TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 2 PSR2 1 PSR1 0 PSR0 * Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 * Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT * Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin * Bit 5 (TS) TCC signal source 0: internal instruction cycle clock 1: transition on TCC pin When TS is 1, the R62 I/O control bit will set to 1; otherwise, it will be the value defined by user. * Bit 6 (INT) Interrupt enable flag 0: masked by DISI or hardware interrupt This specification is subject to change without prior notice. 10 2002/03/01 EM78P153E OTP ROM 1: enabled by ENI/RETI instructions * Bit 7 Not used. * CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) * "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. * Only the lower 4 bits of IOC5 are available to be defined. * IOC5 and IOC6 registers are both readable and writable. 4. IOCB (Pull-down Control Register) 7 6 /PD6 5 /PD5 4 /PD4 3 2 /PD2 1 /PD1 0 /PD0 * Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin. 0: Enable internal pull-down 1: Disable internal pull-down * Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin. * Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin. * Bit 3 Not used. * Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin. * Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin. * Bit 6 (/PD6) Control bit is used to enable the pull-down of P62 pin. * Bit 7 Not used. * IOCB Register is both readable and writable. 5. IOCC (Open-drain Control Register) 7 OD7 6 OD6 5 OD5 4 OD4 3 2 OD2 1 OD1 0 OD0 * Bit 0 (OD0) Control bit is used to enable the open-drain of P60 pin. 0: Disable open-drain output 1: Enable open-drain output * Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin. * Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin. * Bit 3 Not used. * Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin. * Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. * Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin. * Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin. This specification is subject to change without prior notice. 11 2002/03/01 EM78P153E OTP ROM * IOCC Register is both readable and writable. 6. IOCD (Pull-high Control Register) 7 /PH7 6 /PH6 5 /PH5 4 /PH4 3 2 /PH2 1 /PH1 0 /PH0 * Bit 0 (/PH0) Control bit used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable internal pull-high * Bit 1 (/PH1) Control bit is used to enable the pull-high of P61 pin. * Bit 2 (/PH2) Control bit is used to enable the pull-high of P62 pin. * Bit 3 Not used. * Bit 4 (/PH4) Control bit is used to enable the pull-high of P64 pin. * Bit 5 (/PH5) Control bit is used to enable the pull-high of P65 pin. * Bit 6 (/PH6) Control bit is used to enable the pull-high of P66 pin. * Bit 7 (/PH7) Control bit is used to enable the pull-high of P67 pin. * IOCD Register is both readable and writable. 7. IOCE (WDT Control Register) 7 WDTE 6 EIS 5 4 3 2 1 0 - * Bit 7 (WDTE) Control bit used to enable Watchdog timer. 0: Disable WDT. 1: Enable WDT. WDTE is both readable and writable. * Bit 6 (EIS) Control bit is used to define the function of P60(/INT) pin. 0: P60, bi-directional I/O pin. 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 7. EIS is both readable and writable. * Bits 0~5 Not used. 8. IOCF (Interrupt Mask Register) 7 6 5 4 3 2 EXIE 1 ICIE 0 TCIE * Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt This specification is subject to change without prior notice. 12 2002/03/01 EM78P153E OTP ROM 1: enable TCIF interrupt * Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt * Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt * Bits 3~7 Not used. * Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". * Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 9. * IOCF register is both readable and writable. 4.3 TCC/WDT & Prescaler There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the "WDTC" or "SLEP" instructions. Fig. 5 depicts the circuit diagram of TCC/WDT. * R1(TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4, depends on the CODE Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source is from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. * The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms 1 (default). 1 This specification is subject to change without prior notice. 13 2002/03/01 EM78P153E OTP ROM 4.4 I/O Ports The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled-high internally by software except P63. In addition, Port 6 can also have open-drain output by software except P63. Input status changed interrupt (or wake-up) function is available from Port 6. P50 ~ P52 and P60 ~ P62 pins can be pulled-down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6) except P63. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in Fig. 6, Fig.7, and Fig. 8 respectively. CLK(Fosc/2 or Fosc/4) Data Bus 0 TCC Pin 1 TE TS M U X 1 0 M U X SYNC 2 cycles TCC(R1) PAB TCC Overflow Interrupt 0 WDT 1 M U X 8-bit Counter PSR0~PSR2 8-to-1 MUX PAB WDTE (in lOCE) 0 1 MUX PAB WDT Time Out Fig. 5 Block Diagram of TCC and WDT This specification is subject to change without prior notice. 14 2002/03/01 EM78P153E OTP ROM PCRD Q _ Q P R C L D CLK PCWR PORT Q _ Q P R C L D CLK PDWR IOD PDRD 0 1 M U X *Pull-down is not shown in the figure. Fig. 6 The Circuit of I/O Port and I/O Control Register for Port 5 PCRD Q _ Q PD R CLK C L PCWR P60 /INT PORT Bit 6 of IOCE D PQ R CLK _ CQ L 0 1 M U X Q _ Q P RD CLK C L IOD PDWR PDRD T10 D P RQ CLK _ CQ L INT *Pull-high (down), Open-drain are not shown in the figure. Fig. 7 The Circuit of I/O Port and I/O Control Register for P60(/INT) This specification is subject to change without prior notice. 15 2002/03/01 EM78P153E OTP ROM PCRD Q _ Q P RD CLK C L PCWR P61~P67 PORT Q _ Q 0 1 P RD CLK C L IOD PDWR M U X PDRD TIN D P R CLK C L Q _ Q *Pull-high (down), Open-drain are not shown in the figure. Fig. 8 The Circuit of I/O Port and I/O Control Register for P61~P67 IOCE.1 DPQ R CLK Interrupt _ CQ L RE.1 ENI Instruction T10 T11 P DRQ CLK _ CQ L QPD R CLK _ QC L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Fig. 9 Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up This specification is subject to change without prior notice. 16 2002/03/01 EM78P153E OTP ROM Table 2 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 Input Status Change Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (II) Port 6 Input Status Change Interrupt (a) Before SLEEP 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1) 3. Execute "ENI" or "DISI" 4. IF Port 6 change (interrupt) 4. Enable interrupt (Set IOCF.1) Interrupt vector (008H) 5. Execute "SLEP" instruction (b) After Wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction 4.5 RESET and Wake-up 1. RESET A RESET is initiated by (1) Power on reset. (2) /RESET pin input "low", or (3) WDT time-out (if enabled). The device is kept in a RESET condition for a period of approx. 18ms 1 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig.9. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * All I/O port pins are configured as input mode (high-impedance state). * The Watchdog timer and prescaler are cleared. * When power is switched on, the upper 3 bits of R3 are cleared. * The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag). * The bits of the IOCB register are set to all "1". * The IOCC register is cleared. * The bits of the IOCD register are set to all "1". * Bit 7 of the IOCE register is set to "1", and 6 is cleared. * Bits 0~2 of RF and Bits 0~2 of IOCF register are cleared. 1 This specification is subject to change without prior notice. 17 2002/03/01 EM78P153E OTP ROM The sleep (power down) mode is attained by executing the "SLEP" instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by (1) External reset input on /RESET pin, (2) WDT time-out (if enabled), or (3) Port 6 input status changes (if enabled). The first two cases will cause the EM78P153E to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" o "DISI" being executed) decides whether or not the r controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-up. If DISI is executed before SLEP, the operation will restart from the instruction right next to SLEP after wake-up. Only one of Cases 2 and 3 can be enabled before entering the sleep mode. That is, [a] if Port 6 input status changed interrupt is enabled before SLEP , WDT must be disabled. by software. However, the WDT bit in the option register remains enabled. Hence, the EM78P153E can be awakened only by Case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the EM78P153E can be awakened only by Case 1 or 2. Refer to the section on Interrupt. If Port 6 Input Status Change Interrupt is used to wake-up the EM78P153E (Case [a] above), the following instructions must be executed before SLEP: MOV A, @xxxx1110b CONTW WDTC MOV A, @0xxxxxxxb IOW RE MOV R6, R6 MOV A, @00000x1xb IOW RF ENI (or DISI) SLEP ; Select WDT prescaler ; Clear WDT and prescaler ; Disable WDT ; Read Port 6 ; Enable Port 6 input change interrupt ; Enable (or disable) global interrupt ; Sleep One problem user should be aware of, is that after waking up from the sleep mode, WDT will enable automatically. The WDT operation (being enabled or disabled) should be handled appropriately by software after waking up from sleep mode. This specification is subject to change without prior notice. 18 2002/03/01 EM78P153E OTP ROM Table 3 The Summary of the Initialized Values for Registers Address N/A Name IOC5 Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name N/A CONT Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On Bit 7 X 0 0 0 C67 1 1 P X 1 P P P67 1 P P X 0 0 0 U P P 0 0 P 0 0 *P RST 0 0 1 GP2 U P P X 0 0 0 X 1 19 N/A IOC6 0x05 P5 0x06 P6 Bit 6 X 0 0 0 C66 1 1 P X 1 P P P66 1 P P /INT 0 0 P U P P 0 0 P 0 0 *P GP1 U P P GP1 U P P X 0 0 0 /PD6 1 Bit 5 X 0 0 0 C65 1 1 P X 1 P P P65 1 P P TS 1 1 P U P P 0 0 P 0 0 *P GP0 U P P GP0 U P P X 0 0 0 /PD5 1 Bit 4 X 0 0 0 C64 1 1 P X 1 P P P64 1 P P TE 1 1 P U P P 0 0 P 0 0 *P T 1 t t U P P X 0 0 0 /PD4 1 Bit 3 C53 1 1 P C63 1 1 P P53 1 P P P63 1 P P PAB 1 1 P U P P 0 0 P 0 0 *P P 1 t t U P P X 0 0 0 X 1 0x00 R0(IAR) 0x01 R1(TCC) 0x02 R2(PC) 0x03 R3(SR) 0x04 R4(RSR) 0x0F RF(ISR) 0x0B IOCB Bit 0 C50 1 1 P C60 1 1 P P50 1 P P P60 1 P P PSR PSR2 PSR1 0 1 1 1 1 1 1 P P P U U U P P P P P P 0 0 0 0 0 0 P P P 0 0 0 0 0 0 *P *P *P Z DC C U U U P P P P P P U U U P P P P P P EXIF ICIF TCIF 0 0 0 0 0 0 P P P /PD2 /PD1 /PD0 1 1 1 2002/03/01 Bit 2 C52 1 1 P C62 1 1 P P52 1 P P P62 1 P P Bit 1 C51 1 1 P C61 1 1 P P51 1 P P P61 1 P P This specification is subject to change without prior notice. EM78P153E OTP ROM Address Name 0x0C IOCC 0x0D IOCD 0x0E IOCE 0x0F IOCF 0x10~0x2F R10~R2F Reset Type /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit 7 1 P OD7 0 0 P /PH7 1 1 P WDTE 1 1 P X 1 1 1 U P P Bit 6 1 P OD6 0 0 P /PH6 1 1 P EIS 0 0 P X 1 1 1 U P P Bit 5 1 P OD5 0 0 P /PH5 1 1 P X 1 1 1 X 1 1 1 U P P Bit 4 1 P OD4 0 0 P /PH4 1 1 P X 1 1 1 X 1 1 1 U P P Bit 3 1 P X 0 0 P X 1 1 P X 1 1 1 X 1 1 1 U P P Bit 2 1 P OD2 0 0 P /PH2 1 1 P X 1 1 1 EXIE 0 0 P U P P Bit 1 Bit 0 1 1 P P OD1 OD0 0 0 0 0 P P /PH1 /PH0 1 1 1 1 P P X X 1 1 1 1 1 1 ICIE TCIE 0 0 0 0 P P U U P P P P X: not used. U: unknown or don't care. P: previous value before reset. t: check Table 4 2. /RESET Configure Refer to Fig. 10 When the RESET bit in the OPTION word is programmed to 0, the external /RESET is enabled. When programmed to 1, the internal /RESET is enabled, tied to the internal Vdd and the pin is defined as P63. 3. The status of RST, T, and P of STATUS register A RESET condition is initiated by the following events: 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of RST, T, and P, listed in Table 4 are used to check how the processor wakes up. Table 5 shows the events which may affect the status of RST, T, and P. This specification is subject to change without prior notice. 20 2002/03/01 EM78P153E OTP ROM Table 4 The Values of RST, T and P after RESET Reset Type Power on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-Up on pin change during SLEEP mode *P: Previous status before reset Table 5 The Status of RST, T and P Being Affected by Events. Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode *P: Previous value before reset VDD RST 0 0 0 0 0 1 T 1 *P 1 0 0 1 P 1 *P 0 P 0 0 RST 0 *P 0 *P 1 T 1 1 0 1 1 P 1 1 *P 0 0 Oscillator D CLK CLR Q CLK Power-on Reset Voltage Detector WDTE WDT WDT Timeout Setup Time RESET /RESET Fig. 10 Block Diagram of Controller Reset This specification is subject to change without prior notice. 21 2002/03/01 EM78P153E OTP ROM 4.6 Interrupt The EM78P153E has three falling-edge interrupts as listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changes. Any pin configured as output or P60 pin configured as /INT, is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the EM78P153E from sleep mode if Port 6 is enabled prior to going into the sleep mode by executing SLEP instruction. When the chip wakes-up, the controller will continue to execute the program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will branch to the interrupt vector 008H. RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to Fig. 11). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from address 001H. This specification is subject to change without prior notice. 22 2002/03/01 EM78P153E OTP ROM VCC D /IRQn CLK P R C L Q _ Q RFRD IRQn INT IRQm ENI/DISI RF Q _ Q P R C L D CLK IOCFWR IOD IOCF /RESET IOCFRD RFWR Fig. 11 Interrupt Input Circuit 4.7 Oscillator 1. Oscillator Modes The EM78P153E can be operated in four different oscillator modes, such as Internal RC oscillator mode (IRC), External RC oscillator mode (ERC), High XTAL oscillator mode(HXT), and Low XTAL oscillator mode(LXT). User can select one of them by programming OCS1 and OSC2 in the CODE Option register. Table 6 depicts how these four modes are defined. The up-limited operation frequency of crystal/resonator on the different VDDs is listed in Table 7. Table 6 Oscillator Modes Defined by OSC1 and OSC2 Mode IRC(Internal RC oscillator mode) ERC(External RC oscillator mode) HXT(High XTAL oscillator mode) LXT(Low XTAL oscillator mode) OSC1 1 1 0 0 OSC2 1 0 1 0 This specification is subject to change without prior notice. 23 2002/03/01 EM78P153E OTP ROM Table 7 The Summary of Maximum Operating Speeds Conditions Two cycles with two clocks VDD 2.3 3.0 5.0 Fxt max.(MHz) 4.0 8.0 20.0 2. Crystal Oscillator/Ceramic Resonators(XTAL) EM78P153E can be driven by an external clock signal through the OSCI pin as shown in Fig. 12. OSCI OSCO EM78P153E Ext. Clock Fig. 12 Circuit for External Clock Input In most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 13 depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. Table 8 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode. C1 OSCI EM78P153E OSCO XTAL RS C2 Fig. 13 Circuit for Crystal/Resonator This specification is subject to change without prior notice. 24 2002/03/01 EM78P153E OTP ROM Table 8 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz 100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15 LXT Crystal Oscillator HXT 330 330 OSCI 7404 EM78P153E X T 7404 C 7404 Fig. 14 Circuit for Crystal/Resonator-Series Mode 7404 OSCI 4.7K 10K Vdd 7404 EM78P153E 10K X T C 1 C 2 10K Fig. 15 Circuit for Crystal/Resonator-Parallel Mode This specification is subject to change without prior notice. 25 2002/03/01 EM78P153E OTP ROM 3. External RC Oscillator Mode For some applications that do not need to have its timing to be calculated precisely, the RC oscillator (Fig. 16) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the reasons above, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency. Vcc Rext OSCI Cext EM78P153E Fig. 16 Circuit for External RC Oscillator Mode This specification is subject to change without prior notice. 26 2002/03/01 EM78P153E OTP ROM Table 9 RC Oscillator Frequencies Cext Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k Average Fosc 5V,25C 3.92 MHz 2.67 MHz 1.4MHz 150 KHz 1.4 MHz 940 KHz 476 KHz 50KHz 595 KHz 400 KHz 200 KHz 20.9 KHz Average Fosc 3V,25C 3.63 MHz 2.6 MHz 1.4 MHz 156 KHz 1.33 MHz 917 KHz 480 KHz 52 KHz 570 KHz 384 KHz 203 KHz 20 KHz 20 pF 100 pF 300 pF 1. Measured on DIP packages. 2. Design reference only. 4. Internal RC Oscillator Mode EM78P153E offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, and 455KHz) that can be set by OPTION bits, RCM1 and RCM0. All these four main frequencies can be calibrated by programming the OPTION bits, CAL0~CAL2. Table 10 describes a typical instance of the calibration. Table 10 Calibration Selection for Internal RC Mode C2 1 1 0 0 1 1 0 0 C1 0 0 0 0 1 1 1 1 C0 1 0 1 0 1 0 1 0 *Cycle Time (ns) 200.4 211.9 223.7 236.4 250.0 264.6 279.3 295.0 *Frequency (MHz) 4.99 4.72 4.47 4.23 4.00 3.78 3.58 3.39 *:Theoretical values, for reference only. It depend on process. 4.8 CODE Option Register The EM78P153E has one CODE option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: This specification is subject to change without prior notice. 27 2002/03/01 EM78P153E OTP ROM Word 0 Bit12~Bit0 Word1 Bit1~Bit0 Word 2 Bit12~Bit0 Code Option Register (Word 0) WORD 0 Bit7 Bit6 7 CS 6 SUT1 Bit12 12 /RESET Bit11 11 /ENWDT Bit10 10 CLKS Bit9 9 OSC1 Bit8 8 OCS0 Bit5 5 SUT0 Bit4 4 TYPE Bit3 3 RCOUT Bit2 2 C2 Bit1 1 C1 Bit0 0 C0 * Bit 12 (/RESET): Define pin7 as a reset pin. 0: /RESET enable 1: /RESET disable * Bit 11 (/ENWTD): Watchdog timer enable bit. 0: Enable 1: Disable * Bit 10 (CLKS): Instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. Refer to the section of Instruction Set. * Bit 9 and Bit 8 (OSC1 and OSC0 ): Oscillator Modes Selection bits. Table 11 Oscillator Modes Defined by OSC1 and OSC0 Mode IRC(Internal RC oscillator mode) ERC(External RC oscillator mode) HXT(High XTAL oscillator mode) LXT(Low XTAL oscillator mode) OSC1 1 1 0 0 OSC0 1 0 1 0 *:The theoretical values are for reference only. This specification is subject to change without prior notice. 28 2002/03/01 EM78P153E OTP ROM * Bit 2, Bit 1, and Bit 0 ( CAL2, CAL1, CAL 0 ): Calibrator of internal RC mode Bit 3 Table 13 Calibration Selection for Internal RC Mode C2 1 1 0 0 1 1 0 0 C1 0 0 0 0 1 1 1 1 C0 1 0 1 0 1 0 1 0 *Cycle Time (ns) 200.4 211.9 223.7 236.4 250.0 264.6 279.3 295.0 *Frequency (MHz) 4.99 4.72 4.47 4.23 4.00 3.78 3.58 3.39 *: 1. Theoretical values, an instance of the high frequency mode, are shown for reference only, It depend on process. 2. Similar way of calculation is also applicable for low frequency mode. 3. Code Option Register (Word 1) WORD1 Bit1 1 RCM1 RCM 1 1 0 0 RCM 0 1 1 0 Bit0 0 RCM0 *Frequency(MHz) 4 1 455kHz Bit 1, and Bit 0 ( RCM1, RCM0): RC mode selection bits 4. Customer ID Register (Word 2) Bit 12~Bit 0 XXXXXXXXXXXXX Bit 12~ 0 : Customer's ID code 4.9 Power On Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its steady state. This specification is subject to change without prior notice. 29 2002/03/01 EM78P153E OTP ROM EM78P153E is equipped with Power On Voltage Detector (POVD) with a detecting level of 2.0 V. The extra external reset circuit will work well if Vdd rises quick enough (50 ms or less). In many critical applications however, extra devices are still required to assist in solving power-up problems. 4.10 Programmable Oscillator Set-Up Time The Option word contains SUT0 and SUT1, which can be used to define the oscillator set up time. Theoretically, the range is from 4.5 ms to 72 ms. For most of crystal or ceramic resonators, the lower the operation frequency is, the longer the Set-up time may be required. Table 12 describes the values of Oscillator Set-Up Time. 4.11 External Power 0n Reset Circuit The circuit shown in Fig 17 implements an external RC to produce the reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reach minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be great than 40 K. In this way, the voltage in pin /RESET will be held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C, will discharged rapidly and fully. Rl, the current-limited resistor, will prevent high current discharge or ESD (electrostatic discharge) from flowing to pin /RESET. Vdd /RESET R D EM78P153E Rin C Fig. 17 External Power-Up Reset Circuit 4.12 Residue-Voltage Protection When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power This specification is subject to change without prior notice. 30 2002/03/01 EM78P153E OTP ROM on reset. Fig.18 and Fig. 19 show how to build a residue-voltage protection circuit. Vdd Vdd 33K EM78P153E /RESET Q1 10K 100K 1N4684 Fig. 18 Circuit 1 for the Residue Voltage Protection Vdd Vdd R1 EM78P153E /RESET Q1 R3 R2 Fig. 19 Circuit 2 for the Residue Voltage Protection 4.13 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) Modify one instruction cycle to consist of 4 oscillator periods. This specification is subject to change without prior notice. 31 2002/03/01 EM78P153E OTP ROM (B) Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", "RETI" commands, or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. The instructions that are written to the program counter, should also take two instruction cycles. The Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle will consist of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high. The Case (B) is selected by another CODE Option bit, called CYES. Execution of the instructions listed in Case (B) takes one instruction cycle if CYES is low, and takes two instruction cycles if CYES is high. Case (A) and Case (B) are independent options, that is, they can be selected separately. Note that once the 4 oscillator periods within one instruction cycle is selected under Case (A), the internal clock source to TCC will be CLK=Fosc/4 (not Fosc/ 2) as illustrated in Fig. 5. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "R", and affects the operation. "k" represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A A R 0A 0R R-A A R-A R R-1 A R-1 R A VR A 32 STATUS AFFECTED None C None T,P T,P None 2002/03/01 This specification is subject to change without prior notice. EM78P153E OTP ROM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0 0 0 0 0 0 0111 0111 0111 100b 101b 110b 111b 01rr 10rr 11rr bbrr bbrr bbrr bbrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 1 00kk kkkk kkkk 1 1 1 1 1 01kk 1000 1001 1010 1011 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1111 kkkk kkkk A VR R A&RA A&RR A R A A R R A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA A k A A&kA A k A k A, [Top of Stack] PC k-A A PC+1 [SP], 001H PC k+A A Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None None None This specification is subject to change without prior notice. 33 2002/03/01 EM78P153E OTP ROM 4.14 Timing Diagram AC Test Input/Output Waveform 2.4 2.0 TEST POINTS 2.0 0.8 0.8 0.4 AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc This specification is subject to change without prior notice. 34 2002/03/01 EM78P153E OTP ROM 5. ABSOLUTE MAXIMUNM RATINGS Items Temperature under bias Storage temperature Input voltage Output voltage Rating 0C to 70C -65C to 150C -0.3V to +6.0V -0.3V to +6.0V This specification is subject to change without prior notice. 35 2002/03/01 EM78P153E OTP ROM 6. ELECTRICAL CHARACTERISTIC 6.1 DC ELECTRICAL CHARACTERISTIC ( Ta= 0C ~ 70 C, VDD= 5.0V5%, VSS= 0V ) Symbol Parameter XTAL: VDD to 3V FXT XTAL: VDD to 5V ERC ERC: VDD to 5V IIL Input Leakage Current for input pins VIH1 Input High Voltage (VDD=5.0V) VIL1 Input Low Voltage (VDD=5.0V) Input High Threshold Voltage VIHT1 (VDD=5.0V) Input Low Threshold Voltage VILT1 (VDD=5.0V) VIHX1 Clock Input High Voltage VDD=5.0V) VILX1 Clock Input Low Voltage(VDD=5.0V) VIH2 Input High Voltage (VDD=3V) VIL2 VIHT2 VILT2 Input Low Voltage (VDD=3V) Input High Threshold Voltage (VDD=3V) Input Low Threshold Voltage (VDD=3V) Condition Two cycle with two clocks Two cycle with two clocks R: 5K, C: 39 pF VIN = VDD, VSS Ports 5, 6 Ports 5, 6 /RESET, TCC /RESET, TCC OSCI OSCI Ports 5, 6 Ports 5, 6 /RESET, TCC /RESET, TCC OSCI OSCI IOH = -12.0 mA IOL = 12.0 mA -50 25 -100 50 2.4 0.4 0.4 -240 120 4 1 15 15 30 1.5 0.6 1.5 0.4 2.5 1.0 1.5 0.4 Min DC DC F20% 2.0 2.0 0.8 Typ. Max Unit 8.0 MHz 20.0 MHz F20% KHz 1 A V 0.8 V V V V V V V V V V V V V V A A A A A A mA mA 602 VIHX2 Clock Input High Voltage (VDD=3V) VILX2 VOH1 VOL1 VOL2 IPH IPD ISB2 ISB1 ICC1 Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5, 6) Output Low Voltage (P50~P53, P60~P63, P66~P67) Output Low Voltage (P64,P65) Pull-high current Pull-down current ICC2 ICC3 ICC4 IOL = 16.0 mA Pull-high active, input pin at VSS Pull-down active, input pin at VDD All input and I/O pins at VDD, output pin Power down current floating, WDT enabled All input and I/O pins at VDD, output pin Power down current floating, WDT disabled /RESET= 'High', Fosc=32KHz (Crystal Operating supply current (VDD=3V) type,CLK="0"), output pin floating, WDT at two cycles/four clocks disabled /RESET= 'High', Fosc=32KHz (Crystal Operating supply current (VDD=3V) type,CLK="0"), output pin floating, WDT at two cycles/four clocks enabled Operating supply current /RESET= 'High', Fosc=2MHz (Crystal (VDD=5.0V) at two cycles/two clocks type, CLK="0"), output pin floating Operating supply current /RESET= 'High', Fosc=4MHz (Crystal (VDD=5.0V) at two cycles/four type, CLK="0"), output pin floating clocks 19 35 2.0 4.0 This specification is subject to change without prior notice. 36 2002/03/01 EM78P153E OTP ROM 6.2 AC Electrical Characteristic (Ta=0C ~ 70 C, VDD=5V5%, VSS=0V) Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLK="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Cload=20pF Ta = 25C Ta = 25C Ta = 25C Crystal type RC type Conditions Min 45 100 500 (Tins+20)/N* 9 2000 4.5 18 0 20 50 72 18 30 Typ 50 Max 55 DC DC Unit % ns ns ns ms ns ms ms ms ms * N= selected prescaler ratio. * The duration of watch dog timer is determined by option code (Bit6, Bit5). This specification is subject to change without prior notice. 37 2002/03/01 EM78P153E OTP ROM Appendix Package Types: OTP MCU EM78P153EP EM78P153EN Package Type DIP SOP Pin Count 14 14 Package Size 300 mil 150 mil This specification is subject to change without prior notice. 38 2002/03/01 |
Price & Availability of EM78P153E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |